View LTC1749IFW_4796693.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC1749 12-Bit, 80Msps Wide Bandwidth ADC DESCRIPTIO
The LTC(R)1749 is an 80Msps, 12-bit A/D converter designed for digitizing wide dynamic range signals up to frequencies of 500MHz. The input range of the ADC can be optimized with the on-chip PGA sample-and-hold circuit and flexible reference circuitry. The LTC1749 has a highly linear sample-and-hold circuit with a bandwidth of 500MHz. The SFDR is 80dB with an input frequency of 250MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with minimal degradation in SNR. DC specs include 1LSB INL and no missing codes. The digital interface is compatible with 5V, 3V, 2V and LVDS logic systems. The ENC and ENC inputs may be driven differentially from PECL, GTL and other low swing logic families or from single-ended TTL or CMOS. The low noise, high gain ENC and ENC inputs may also be driven by a sinusoidal signal without degrading performance. A separate output power supply can be operated from 0.5V to 5V, making it easy to connect directly to low voltage DSPs or FIFOs. The 48-pin TSSOP package with a flow-through pinout simplifies the board layout.
, LTC and LT are registered trademarks of Linear Technology Corporation.
FEATURES
s s s s s s s s s s s s
Sample Rate: 80Msps PGA Front End (2.25VP-P or 1.35VP-P Input Range) 71.8dB SNR and 87dB SFDR (PGA = 0) 70.2dB SNR and 87dB SFDR (PGA = 1) 500MHz Full Power Bandwidth S/H No Missing Codes Single 5V Supply Power Dissipation: 1.45W Two Pin Selectable Reference Values Data Ready Output Clock Pin Compatible 14-Bit 80Msps Device (LTC1750) 48-Pin TSSOP Package
APPLICATIO S
s s s s s s s
Direct IF Sampling Telecommunications Receivers Cellular Base Stations Spectrum Analysis Communications Test Equipment Undersampling
BLOCK DIAGRA
PGA AIN+
80Msps, 12-Bit ADC with a 2.25V Differential Input Range
OVDD 0.1F S/H CIRCUIT 12-BIT PIPELINED ADC CORRECTION LOGIC AND SHIFT REGISTER 12 OUTPUT LATCHES * * * D11 D0 CLKOUT 0.5V TO 5V 0.1F
1.125V DIFFERENTIAL - ANALOG INPUT AIN SENSE BUFFER
RANGE SELECT
DIFF AMP GND CONTROL LOGIC
1749 BD
VCM 4.7F
2VREF
REFLB 0.1F 1F
REFHA 4.7F
REFLA
REFHB 0.1F
ENC
ENC
1F
DIFFERENTIAL ENCODE INPUT
U
W
U
OGND
VDD 1F 1F
5V 1F
MSBINV
1749f
1
LTC1749
ABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW SENSE VCM GND AIN+ AIN- GND VDD VDD GND REFLB REFHA GND GND REFLA REFHB GND VDD VDD GND VDD GND MSBINV ENC ENC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FW PACKAGE 48-LEAD PLASTIC TSSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 OF OGND D11 D10 D9 OVDD D8 D7 D6 D5 OGND GND GND D4 D3 D2 OVDD D1 D0 NC NC OGND CLKOUT PGA
Supply Voltage (VDD) ............................................. 5.5V Analog Input Voltage (Note 3) .... - 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) ..... - 0.3V to (VDD + 0.3V) Digital Output Voltage ................. - 0.3V to (VDD + 0.3V) OGND Voltage ..............................................- 0.3V to 1V Power Dissipation ............................................ 2000mW Operating Temperature Range LTC1749C ............................................... 0C to 70C LTC1749I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1749CFW LTC1749IFW
TJMAX = 150C, JA = 35C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Full-Scale Tempco Offset Tempco Input Referred Noise (Transition Noise) CONDITIONS
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
q
(Note 6)
q q
(Note 7) External Reference (VSENSE = 1.125V, PGA = 0) External Reference (VSENSE = 1.125V, PGA = 0) Internal Reference External Reference (VSENSE = 1.125V) VSENSE = 1.125V, PGA = 0
MIN 12 - 1.0 -1.5 -0.8 -35 -3.5
TYP 0.4 0.2 8 1 40 20 20 0.23
MAX 1.0 1.5 0.8 35 3.5
UNITS Bits LSB LSB LSB mV %FS ppm/C ppm/C V/C LSBRMS
A ALOG I PUT
SYMBOL VIN IIN CIN tACQ tAP tJITTER CMRR
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
PARAMETER Analog Input Range (Note 8) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio CONDITIONS 4.75V VDD 5.25V 0 < AIN+, AIN- < VDD Sample Mode ENC < ENC Hold Mode ENC > ENC MIN
q q
-1
q
1.5V < (AIN- = AIN+) < 3V
TYP MAX 0.7 to 1.125 1 6.9 2.4 5 6 0 0.15 80
UNITS V A pF pF ns ns psRMS dB
1749f
2
U
W
U
U
WW
W
U
U
U
LTC1749
DY A IC ACCURACY
SYMBOL SNR PARAMETER Signal-to-Noise Ratio
SFDR
S/(N + D)
THD
IMD
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V 1mA IOUT 1mA
U
WU
U
TA = 25C, AIN = -1dBFS (Note 5), VSENSE = VDD
CONDITIONS 5MHz Input Signal (PGA = 0) 5MHz Input Signal (PGA = 1) 30MHz Input Signal (PGA = 0) 30MHz Input Signal (PGA = 1) 70MHz Input Signal (PGA = 0) 70MHz Input Signal (PGA = 1) 140MHz Input Signal (PGA = 1) 250MHz Input Signal (PGA = 1) 350MHz Input Signal (PGA = 1) 70.5 MIN TYP 71.8 70.2 71.7 70.2 71.4 70.1 69.8 69.3 67.4 87 87 76 83 76 83 87 90 85 87 90 84 80 74 71.7 70.1 71.6 70.0 71.2 69.9 68.6 -87 -87 -87 -87 -85 -87 78 -87 -87 500 MAX UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBc dBc MHz
68.8
Spurious Free Dynamic Range
5MHz Input Signal (PGA = 0) 5MHz Input Signal (PGA = 1) 30MHz Input Signal (PGA = 0) (HD2 and HD3) 30MHz Input Signal (PGA = 0) (Other) 70MHz Input Signal (PGA = 0) 70MHz Input Signal (PGA = 1) (HD2 and HD3) 70MHz Input Signal (PGA = 1) (Other) 140MHz Input Signal (PGA = 1) 250MHz Input Signal (PGA = 1) 350MHz Input Signal (PGA = 1)
Signal-to-(Noise + Distortion) Ratio
5MHz Input Signal (PGA = 0) 5MHz Input Signal (PGA = 1) 30MHz Input Signal (PGA = 0) 30MHz Input Signal (PGA = 1) 70MHz Input Signal (PGA = 0) 70MHz Input Signal (PGA = 1) 250MHz Input Signal (PGA = 1)
Total Harmonic Distortion
5MHz Input Signal, First 5 Harmonics (PGA = 0) 5MHz Input Signal, First 5 Harmonics (PGA = 1) 30MHz Input Signal, First 5 Harmonics (PGA = 0) 30MHz Input Signal, First 5 Harmonics (PGA = 1) 70MHz Input Signal, First 5 Harmonics (PGA = 0) 70MHz Input Signal, First 5 Harmonics (PGA = 1) 250MHz Input Signal (PGA = 1)
Intermodulation Distortion Sample-and-Hold Bandwidth
fIN1 = 2.52MHz, fIN2 = 5.2MHz (PGA = 0) fIN1 = 2.52MHz, fIN2 = 5.2MHz (PGA = 1) RSOURCE = 50
U
(Note 5)
MIN 1.95 TYP 2 30 3 4 MAX 2.05 UNITS V ppm/C mV/V
1749f
3
LTC1749 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN VOH VOL ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Output Source Current Output Sink Current CONDITIONS VDD = 5.25V, MSBINV and PGA VDD = 4.75V, MSBINV and PGA VIN = 0V to VDD MSBINV and PGA Only OVDD = 4.75V OVDD = 4.75V VOUT = 0V VOUT = 5V IO = -10A IO = - 200A IO = 160A IO = 1.6mA
q q q q q
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN 2.4 0.8 10 1.5 4.74 4 4.74 0.05 0.1 - 50 50 0.4 TYP MAX UNITS V V A pF V V V V mA mA
POWER REQUIRE E TS
SYMBOL VDD IDD PDIS OVDD PARAMETER Positive Supply Voltage Positive Supply Current Power Dissipation Digital Output Supply Voltage
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS q q 0.5 MIN 4.75 290 1.45 TYP MAX 5.25 338 1.69 VDD UNITS V mA W V
TI I G CHARACTERISTICS
SYMBOL t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER ENC Period ENC High ENC Low Aperture Delay ENC to CLKOUT Falling ENC to CLKOUT Rising For 80Msps 50% Duty Cycle ENC to DATA Delay ENC to DATA Delay (Hold Time) ENC to DATA Delay (Setup Time) For 80Msps 50% Duty Cycle CLKOUT to DATA Delay (Hold Time), 80Msps 50% Duty Cycle CLKOUT to DATA Delay (Setup Time), 80Msps 50% Duty Cycle Data Latency
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS (Note 9) (Note 8) (Note 8) (Note 8) CL = 10pF (Note 8) CL = 10pF (Note 8) CL = 10pF (Note 8) CL = 10pF (Note 8) (Note 8) CL = 10pF (Note 8) CL = 10pF (Note 8) (Note 8) CL = 10pF (Note 8) q q q 5.3 6 2.1 5 q q q 7.25 2 1.4 q 1 q q q MIN 12.5 6 6 0 2.4 t1 + t 4 8.65 4.9 3.4 t0 - t 6 7.6 10.5 10.25 7.2 4.7 4 TYP MAX 2000 1000 1000 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns cycles
4
UW
U
U
UW
1749f
LTC1749
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND, they will be clamped by internal diodes. This product can handle input currents of >100mA below GND without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 80MHz, differential ENC/ENC = 2VP-P 80MHz sine wave, input range = 1.125V differential, unless otherwise specified. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar offset is the offset voltage measured from - 0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions.
TYPICAL PERFOR A CE CHARACTERISTICS
INL
1.0 0.8 0.6 0.4 ERROR (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 3072 2048 OUTPUT CODE 4096
1749 G01
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 3072 2048 OUTPUT CODE 4096
1749 G02
AMPLITUDE (dBFS)
ERROR (LSB)
8192 Point FFT, fIN = 15MHz, -10dB, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 0 -10 -20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40
AMPLITUDE (dBFS)
UW
1749 G04
DNL
1.0 0.8 0.6 0.4
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
8192 Point FFT, fIN = 15MHz, -1dB, PGA = 0
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
1749 G03
8192 Point FFT, fIN = 15MHz, -20dB, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
8192 Point FFT, fIN = 30.2MHz, -1dB, PGA = 0
-30 -40
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
1749 G05
1749 G06
1749f
5
LTC1749 TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT, fIN = 30.2MHz, -10dB, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 0 -10 -20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40
AMPLITUDE (dBFS)
8192 Point FFT, fIN = 70.03MHz, -10dB, PGA = 0
0 -10 -20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40
-50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40
AMPLITUDE (dBFS)
-30 -40
8192 Point FFT, fIN = 140.2MHz, -10dB, PGA = 1
0 -10 -20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40
-50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40
AMPLITUDE (dBFS)
-30 -40
6
UW
1749 G07 1749 G10
8192 Point FFT, fIN = 30.2MHz, -20dB, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
8192 Point FFT, fIN = 70.03MHz, -1dB, PGA = 0
-30 -40
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
1749 G08
1749 G09
8192 Point FFT, fIN = 70.03MHz, -20dB, PGA = 0
0 -10 -20 -30 -40 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
8192 Point FFT, fIN = 140.2MHz, -1dB, PGA = 1
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
1749 G11
1749 G12
8192 Point FFT, fIN = 140.2MHz, -20dB, PGA = 1
0 -10 -20 -30 -40 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
8192 Point FFT, fIN = 250.2MHz, -1dB, PGA = 1
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
1749 G13
1749 G14
1749 G15
1749f
LTC1749 TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT, fIN = 250.2MHz, -10dB, PGA = 1
0 -10 -20
AMPLITUDE (dBFS) AMPLITUDE (dBFS)
-50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40
-50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40
AMPLITUDE (dBFS)
-30 -40
8192 Point 2-Tone FFT, 65.01MHz and 70.01MHz, -7dB, PGA = 0
0 -10 -20
SFDR (dBc AND dBFS) AMPLITUDE (dBFS)
70 60 50 40 30 20 10 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
SFDR (dBc AND dBFS)
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40
SFDR vs 140.2MHz, Input Level, PGA = 1
120 100 SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 80 60 40 20 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 120 100 80
SNR (dBFS)
UW
1749 G16 1749 G19
8192 Point FFT, fIN = 250.2MHz, -20dB, PGA = 1
0 -10 -20 -30 -40 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
8192 Point 2-Tone FFT, 25.01MHz and 30.1MHz, -7dB, PGA = 0
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
1749 G17
1749 G18
SFDR vs 30.2MHz Input Level, PGA = 0
110 100 90 80 110 100 90 80 70 60 50 40 30 20 10 0
SFDR vs 70.2MHz, Input Level, PGA = 0
0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
1749 G20
1749G21
SFDR vs 250.2MHz, Input Level
72.0 71.5 71.0 70.5 70.0 69.5 69.0
SNR vs Input Frequency and Amplitude, PGA = 0
-20dB -10dB -1dB
60 40 20 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
68.5 68.0 0 50 100 200 250 150 INPUT FREQUENCY (MHz) 300
1749 G24
0
0
1749 G22
1749 G23
1749f
7
LTC1749 TYPICAL PERFOR A CE CHARACTERISTICS
SNR vs Input Frequency and Amplitude, PGA = 1
71.0 70.5 70.0 69.5 -1dB -20dB -10dB
SFDR (dBFS)
SFDR (dBFS)
SNR (dBFS)
69.0 68.5 68.0 67.5 67.0 66.5 66.0
0
100 300 400 200 INPUT FREQUENCY (MHz)
SFDR and SNR vs Sample Rate, 15.2MHz, -1dB Input
100 95
100 95
SUPPLY CURRENT (mA)
SFDR AND SNR (dBFS)
SFDR AND SNR (dBFS)
90 85 80 75 70 65 60 0 20 80 60 SAMPLE RATE (Msps) 40 100 120
1749 G28
SFDR
SNR
8
UW
1749 G25
SFDR (HD2 and HD3) vs Input Frequency and Amplitude, PGA = 0
100 -10dB -20dB 90 -1dB 80
100
SFDR (HD2 and HD3) vs Input Frequency and Amplitude, PGA = 1
90 -1dB 80 -10dB
-20dB
70
70
60
60
500
0
50
100 150 200 250 INPUT FREQUENCY (MHz)
300
1749 G26
50
0
100 300 400 200 INPUT FREQUENCY (MHz)
500
1749 G27
SFDR and SNR vs VDD, 15.2MHz, -1dB Input
310 300
SFDR 85 80 75 70 65 60 4.1 4.3 4.5 4.7 4.9 VDD (V) 5.1 5.3 5.5 SNR
Supply Current vs Sample Rate
90
290 280 270 260 250 240 0 20 40 60 80 100
1749 G30
SAMPLE RATE (Msps)
1749 G29
1749f
LTC1749
PI FU CTIO S
SENSE (Pin 1): Reference Sense Pin. GND selects a VREF of 0.7V. VDD selects 1.125V. When VSENSE is between 0.7V and 1.125V, VSENSE is used as VREF. The ADC input range is VREF/PGA gain. VCM (Pin 2): 2.0V Output and Input Common Mode Bias. Bypass to ground with 4.7F ceramic chip capacitor. GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power Ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN- (Pin 5): Negative Differential Analog Input. VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND with 1F ceramic chip capacitors at Pin 8 and Pin 18. REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11 with 0.1F ceramic chip capacitor. Do not connect to Pin 14. REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with 0.1F ceramic chip capacitor, to Pin 14 with a 4.7F ceramic capacitor and to ground with 1F ceramic capacitor. REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with 0.1F ceramic chip capacitor, to Pin 11 with a 4.7F ceramic capacitor and to ground with 1F ceramic capacitor. REFHB (Pin 15): ADC High Reference. Bypass to Pin 14 with 0.1F ceramic chip capacitor. Do not connect to Pin 11. MSBINV (Pin 22): MSB Inversion Control. Low inverts the MSB, 2's complement output format. High does not invert the MSB, offset binary output format. ENC (Pin 23): Encode Input. The input sample starts on the positive edge. ENC (Pin 24): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1F ceramic for single-ended ENCODE signal. PGA (Pin 25): Programmable Gain Amplifier Control. Low selects an effective front-end gain of 1. High selects an effective gain of 1 2/3. The ADC input range is VREF/PGA gain. CLKOUT (Pin 26): Data Valid Output. Latch data on the rising edge of CLKOUT. OGND (Pins 27, 38, 47): Output Driver Ground. NC (Pins 28, 29): No Internal Connection. D0, D1 (Pins 30, 31): Digital Outputs. OVDD (Pins 32, 43): Positive Supply for the Output Drivers. Bypass to ground with 0.1F ceramic chip capacitor. D2-D4 (Pins 33 to 35): Digital Outputs. D5-D8 (Pins 39 to 42): Digital Outputs. D9-D11 (Pins 44 to 46): Digital Outputs. OF (Pin 48): Over/Under Flow Output. High when an over or under flow has occurred.
U
U
U
1749f
9
LTC1749 TI I G DIAGRA
N ANALOG INPUT t3 t1 ENC t7 DATA t6 CLKOUT t4 t5 t10 t9
1749 TD
*
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
THD = 20Log V22 + V32 + V 42 + ...Vn2 V1
10
U
W
W
t2 t0 t8 DATA (N - 5) DB11 TO DB0 DATA (N - 4) DB11 TO DB0 DATA (N - 3)
UU
UW
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa - fb and 2fb - fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.
1749f
LTC1749
APPLICATIO S I FOR ATIO
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC equals the ENC voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise
PGA AIN+ AIN- INPUT S/H FIRST PIPELINED ADC STAGE (5 BITS) SECOND PIPELINED ADC STAGE (4 BITS) THIRD PIPELINED ADC STAGE (4 BITS) FOURTH PIPELINED ADC STAGE (2 BITS)
VCM 4.7F
2.0V REFERENCE SHIFT REGISTER AND CORRECTION
RANGE SELECT
REFL SENSE REF BUF
DIFF REF AMP
REFLB REFHA 4.7F 0.1F 1F
Figure 1. Functional Block Diagram
1749f
U
when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2) * FIN * TJITTER CONVERTER OPERATION The LTC1749 is a CMOS pipelined multistep converter with a front-end PGA. The converter has four pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later, see the Timing Diagram section. The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample-and-hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC1749 has two phases of operation, determined by the state of the differential ENC/ENC input pins. For brevity, the text will refer to ENC greater than ENC as ENC high and ENC less than ENC as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier.
REFH INTERNAL CLOCK SIGNALS OVDD 0.5V TO 5V OF D11 CONTROL LOGIC AND CALIBRATION LOGIC OUTPUT DRIVERS DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER D0 CLKOUT
1749 F01
W
UU
REFLA REFHB 0.1F 1F
ENC
ENC
MSBINV
OGND
11
LTC1749
APPLICATIO S I FOR ATIO
In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "Input S/H" shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third stage, resulting in a third stage residue that is sent to the fourth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC1749 CMOS differential sample-and-hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS switches. This direct capacitor sampling results in lowest possible noise for a given sampling capacitor size. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC/ENC is low, the NMOS switch connects the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC/ENC transitions from low to high the
12
U
LTC1749 VDD CSAMPLE 3.5pF CPARASITIC 2.4pF RON 30 RON 30 CPARASITIC 2.4pF 5V CPARASITIC 1pF CSAMPLE 3.5pF AIN+ VDD AIN- CPARASITIC 1pF BIAS 2V 6k ENC ENC 6k 2V
1749 F02
W
UU
Figure 2. Equivalent Input Circuit
sampled input voltage is held on the sampling capacitors. During the hold phase when ENC/ENC is high the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC/ENC transitions from high to low the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing within the valid input range, around a common mode voltage of 2.0V. The VCM output pin (Pin 2) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 4.7F or greater capacitor.
1749f
LTC1749
APPLICATIO S I FOR ATIO
Input Drive Circuits
The LTC1749 requires differential drive for the analog inputs. A balanced input drive will minimize even order harmonics that are due to nonlinear behavior of the input drive circuits and the S/H circuit. The S/H circuit of the LTC1749 is a switched capacitor circuit (Figure 2). The input drive circuitry will see a sampling glitch at the start of the sampling period, when ENC/ENC falls. Although designed to be linear as possible, a small fraction of this glitch is nonlinear and can result in additional observed distortion if the input drive circuitry is too slow. For most practical circuits the glitch nonlinearity is more than 100dB below the fundamental. The glitch will decay during the sampling period with a time constant determined by the input drive and S/H circuitry. For fast settling and wide bandwidth, a low drive impedance is required. The S/H bandwidth is partially determined by the source impedance. The full 500MHz bandwidth is valid for source impedance (each input) less than 30. Higher source impedance can be used but full amplitude distortion will be better with a source impedance less than 100. Transformers Transformers provide a simple method for converting a single-ended signal to a differential signal; however, they have poor performance characteristics at low and high input frequencies. The lower -3dB corner of RF transformers can range from tens of kHz to tens of MHz. Operation near this corner results in poor 2nd order harmonic performance due to nonlinear transformer core behavior. The upper -3dB corner can vary from tens of MHz to several GHz. Operation near the upper corner can result in poor 2nd order performance due to poor balance on the secondary. Transformers should be selected to have -3dB corners at least one octave away from the desired operating frequency. Transformers with larger cores usually have better performance at lower frequency and perform better when driving heavy loads. Figure 3a shows the LTC1749 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC-biased with VCM, setting the ADC input
U
signal at its optimum DC level of 2V. In this example a 1:1 transformer is used; however, other transformer impedance ratios may be substituted. Figure 3b shows the use of a transformer without a center tapped secondary. In this example the secondary is biased with the addition of two resistors placed in series across the secondary winding. The center tap of the secondary resistors is connected to the ADC VCM output to set the DC bias. This circuit is better suited for high input frequency applications since center tapped transformers generally have less bandwidth and poor balance at high frequencies than noncenter tapped transformers.
VCM 4.7F LTC1749 0.1F ANALOG INPUT 100 1:1 25 100 25 12pF 25 AIN+ AIN-
1749 F03
W
UU
12pF 12pF
25
Figure 3a. Single-Ended to Differential Conversion Using a Transformer
VCM 0.1F ANALOG INPUT 100 200 10 25 8.4pF
1749 F03b
4.7F 10 1:4 200 25 8.4pF
LTC1749 AIN+
AIN-
Figure 3b. Using a Transformer Without a Center Tapped Secondary
Active Drive Circuits Active circuits, open loop or closed loop, can be used to drive the ADC inputs. Closed-loop circuits such as op amps have excellent DC and low frequency accuracy but have poor high frequency performance. Figure 4 shows the dual LT(R)1818 op amp used for single-ended to differential signal conversion. Note that the two op amps do not have the same noise gain, which can result in poor balance at higher frequencies. The op amp configured in a gain of +1
1749f
13
LTC1749
APPLICATIO S I FOR ATIO
4.7F 5V SINGLE-ENDED INPUT 2V 1/2 RANGE 12pF 25
VCM
2V VCM 4.7F
+
1/2 LT1818
25 AIN+ LTC1749 12pF
TIE TO VDD FOR VREF = 1.125; TIE TO GND FOR VREF = 0.7V; VREF = VSENSE FOR 0.7V < VSENSE < 1.125V 1F SENSE REFLB 0.1F REFHA BUFFER INTERNAL ADC HIGH REFERENCE RANGE DETECT AND CONTROL VREF
-
100
+
1/2 LT1818
25
25 AIN- 12pF
-
500 500
Figure 4. Differential Drive with Op Amps
can be configured in a noise gain of +2 with the addition of two equal valued resistors between the output and inverting input and between the two inputs. This however will raise the noise contributed by the op amps. Reference Operation Figure 5 shows the LTC1749 equivalent reference circuitry consisting of a 2V bandgap reference, a 3-to-1 switch, a switch control circuit and a difference amplifier. The 2V bandgap reference serves two functions. First, it is assessable at the VCM pin to provide a DC bias point for setting the common mode voltage of any external input circuitry. Second, it is used to derive internal reference levels that may be used to set the input range of the ADC. An external bypass capacitor is required for the 2V reference output at the VCM pin. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference, which will not be stable without this capacitor. To achieve the optimal input range for an application, the internal reference voltage (VREF) is flexible. The reference switch shown in Figure 5 connects VREF to one of two internally derived reference voltages, or to an externally derived reference voltage. The internally derived references are selected by strapping the SENSE pin to GND for 0.7V, or to VDD for 1.125V. When 0.7V > VSENSE > 1.125V,
14
U
LTC1749 4 2V BANDGAP REFERENCE 1.125V 0.7V
1749 F04
W
UU
4.7F DIFF AMP 1F REFLA 0.1F REFHB INTERNAL ADC LOW REFERENCE
1749 F05
Figure 5. Equivalent Reference Circuit
VSENSE is directly connected to VREF. Because of the dual nature of the SENSE pin, driving it with a logic device is not recommended. Reference voltages between 0.7V and 1.125V may be programmed with two external resistors as shown in Figure 6a. An external reference may be used by applying its output directly or through a resistor divider to the SENSE pin (Figure 6b). When the SENSE pin is driven with an externally derived reference voltage, it should be bypassed to ground as close to the device as possible with a 1F ceramic capacitor. A difference amplifier generates the high and low references for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins: REFHA and REFHB for the high reference and REFLA and REFLB for the low reference. The doubled output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 5.
1749f
LTC1749
APPLICATIO S I FOR ATIO
2V VCM 4.7F 10k 1V 10k SENSE 1F LTC1749
1749 F06a
Figure 6a. 2V Range ADC
2V VCM 4.7F 4 6 2.5k 1F 10k SENSE 1F LTC1749
5V 0.1F
LT1790-1.25 1, 2
Figure 6b. 2V Range ADC with External Reference
Input Range The LTC1749 performance may be optimized by adjusting the ADC's input range to meet the requirements of the application. For lower input frequency applications (<40MHz), the highest input range of 1.125V (2.25V) will provide the best SNR while maintaining excellent SFDR. For higher input frequencies (>80MHz), a lower input range will provide better SFDR performance with a reduction in SNR. The input range of the ADC is determined as VREF/APGA, where VREF is the reference voltage (described in the Reference Operation section) and APGA is the effective
Table 1 PGA 0 1 0 1 0 1 VSENSE = VDD = VDD = GND = GND 0.7V < VSENSE < 1.125V 0.7V < VSENSE < 1.125V INPUT RANGE 2.25VP-P Differential 1.35VP-P Differential 1.4VP-P Differential 0.84VP-P Differential 2 x VSENSE Differential 1.2 x VSENSE Differential
U
PGA gain. Table 1 shows the input range of the ADC versus the state of the two pins, PGA and SENSE. Driving the Encode Inputs The noise performance of the LTC1749 can depend on the encode signal quality as much as on the analog input. The ENC/ENC inputs are intended to be driven differentially, primarily for immunity from common mode noise sources. Each input is biased through a 6k resistor to a 2V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.8V to VDD. Each input may be driven from ground to VDD for single-ended drive.
1749 F06b
W
UU
COMMENTS Best Noise, SNR = 71.8dB. Good SFDR, >80dB Up to 100MHz Improved High Frequency Distortion. SNR = 70.5dB. SFDR > 80dB Up to 250MHz Reduced Internal Reference Mode with PGA = 0. Provides Similar Input Range as VSENSE = VDD and PGA = 0 But with Worse Noise. SNR = 70.3dB Smallest Possible Input Span. Useful for Improved Distortion at Very High Frequencies, But with Reduced Noise Performance. SNR = 69dB Adjustable Input Range with Better Noise Performance. SNR = 71.8dB with VSENSE = 1.125V, SNR = 70.3dB with VSENSE = 0.7V Adjustable Input Range with Better High Frequency Distortion. SNR = 70.5dB with VSENSE = 1.125V, SNR = 69dB with VSENSE = 0.7V
1749f
15
LTC1749
APPLICATIO S I FOR ATIO
ANALOG INPUT 0.1F CLOCK INPUT 50 1:4
ENC
ENC
Figure 7. Transformer Driven ENC/ENC
3.3V MC100LVELT22
ENC LTC1749
VTHRESHOLD = 2V
2V ENC 0.1F
1749 F08a
Figure 8a. Single-Ended ENC Drive, Not Recommended for Low Jitter
Maximum and Minimum Encode Rates The maximum encode rate for the LTC1749 is 80Msps. For the ADC to operate properly the encode signal should have a 50% (4%) duty cycle. Each half cycle must have at least 6ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. At sample rates slower than 80Msps the duty cycle can vary from 50% as long as each half cycle is at least 6ns. The lower limit of the LTC1749 sample rate is determined by droop of the sample-and-hold circuits. The pipelined
16
U
LTC1749 5V BIAS 2V BIAS 6k TO INTERNAL ADC CIRCUITS VDD VDD 2V BIAS 6k
1749 F07
W
UU
3.3V 130 Q0 130 ENC LTC1749
D0
Q0 83
ENC 83
1749 F08b
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC1749 is 1Msps. DIGITAL OUTPUTS Digital Output Buffers Figure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damping resistors. 1749f
LTC1749
APPLICATIO S I FOR ATIO
VDD
DATA FROM LATCH
PREDRIVER LOGIC
Figure 9. Equivalent Circuit for a Digital Output Buffer
Output Loading As with all high speed/high resolution converters the digital output loading can affect the performance. The digital outputs of the LTC1749 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43 on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. Format The LTC1749 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MSBINV pin; high selects offset binary. Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. When OF outputs a logic high the converter is either overranged or underranged. Output Clock The ADC has a delayed version of the ENC input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system.
U
LTC1749 VDD OVDD 0.5V TO VDD 0.1F OVDD 43 TYPICAL DATA OUTPUT OGND
1749 F09
W
UU
This is necessary when using a sinusoidal encode. Data will be updated just after CLKOUT falls and can be latched on the rising edge of CLKOUT. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 3V supply then OVDD should be tied to that same 3V supply. OVDD can be powered with any voltage up to 5V. The logic outputs will swing between OGND and OVDD. GROUNDING AND BYPASSING The LTC1749 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. The pinout of the LTC1749 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as shown in the block diagram on the front page of this data
1749f
17
LTC1749
APPLICATIO S I FOR ATIO
sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recomended. The large 4.7F capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1749 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. An analog ground plane separate from the digital processing system ground should be used. All ADC ground pins labeled GND should connect to this plane. All ADC VDD bypass capacitors, reference bypass capacitors and input filter capacitors should connect to this analog plane. The LTC1749 has three output driver ground pins, labeled OGND (Pins 27, 38 and 47). These grounds should connect to the digital processing system ground. The output
18
U
driver supply, OVDD should be connected to the digital processing system supply. OVDD bypass capacitors should bypass to the digital system ground. The digital processing system ground should be connected to the analog plane at ADC OGND (Pin 38). HEAT TRANSFER Most of the heat generated by the LTC1749 is transferred from the die through the package leads onto the printed circuit board. In particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. These pins have the lowest thermal resistance between the die and the outside environment. It is critical that all ground pins are connected to a ground plane of sufficient area. The layout of the evaluation circuit shown on the following pages has a low thermal resistance path to the internal ground plane by using multiple vias near the ground pins. A ground plane of this size results in a thermal resistance from the die to ambient of 35C/W. Smaller area ground planes or poorly connected ground pins will result in higher thermal resistance.
1749f
W
UU
LTC1749
PACKAGE DESCRIPTIO
0.95 0.10
8.1 0.10
6.2 0.10 7.9 - 8.3 (.311 - .327)
0.32 0.05
0.50 TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1.20 (.0473) MAX 0 - 8 -C-T.10 C 0.05 - 0.15 (.002 - .006)
FW48 TSSOP 0502
RECOMMENDED SOLDER PAD LAYOUT 6.0 - 6.2** (.236 - .244)
0.09 - 0.20 (.0035 - .008)
0.45 - 0.75 (.018 - .029)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
FW Package 48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)
12.4 - 12.6* (.488 - .496) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 0.50 (.0197) BSC 0.17 - 0.27 (.0067 - .0106)
1749f
19
LTC1749 RELATED PARTS
PART NUMBER LTC1405 LTC1406 LTC1411 LTC1412 LTC1414 LTC1420 LT 1461 LTC1666 LTC1667 LTC1668 LTC1741 LTC1742 LTC1743 LTC1744 LTC1745 LTC1746 LTC1747 LTC1748 LTC1750 LT1807 LT5512 LT5515 LT5516 LT5522
(R)
DESCRIPTION 12-Bit, 5Msps Sampling ADC with Parallel Output 8-Bit, 20Msps ADC 14-Bit, 2.5Msps ADC 12-Bit, 3Msps, Sampling ADC 14-Bit, 2.2Msps ADC 12-Bit, 10Msps ADC Micropower Precision Series Reference 12-Bit, 50Msps DAC 14-Bit, 50Msps DAC 16-Bit, 50Msps DAC 12-Bit, 65Msps ADC 14-Bit, 65Msps ADC 12-Bit, 50Msps ADC 14-Bit, 50Msps ADC 12-Bit, 25Msps ADC 14-Bit, 25Msps ADC 12-Bit, 80Msps ADC 14-Bit, 80Msps ADC 14-Bit, 80Msps ADC with Wide Bandwidth 325MHz, Low Distortion Dual Op Amp High Signal Level Down Converting Mixer Direct Conversion Demodulator Direct Conversion Quadrature Demodulator High Signal Level Down Converting Mixer
COMMENTS Pin Compatible with the LTC1420 Undersampling Capability up to 70MHz 5V, No Pipeline Delay, 80dB SINAD 5V, No Pipeline Delay, 72dB SINAD 5V, 81dB SINAD and 95dB SFDR 71dB SINAD and 83dB SFDR at Nyquist 0.04% Max Initial Accuracy, 3ppm/C Drift Pin Compatible with the LTC1668, LTC1667 Pin Compatible with the LTC1668, LTC1666 16-Bit Monotonic, 87dB SFDR, 5pV-s Glitch Impulse Pin Compatible with the LTC1743, LTC1745, LTC1747 Pin Compatible with the LTC1744, LTC1746, LTC1748 Pin Compatible with the LTC1741, LTC1745, LTC1747 Pin Compatible with the LTC1742, LTC1746, LTC1748 Pin Compatible with the LTC1741, LTC1743, LTC1747 Pin Compatible with the LTC1742, LTC1744, LTC1748 Pin Compatible with the LTC1741, LTC1743, LTC1745 Pin Compatible with the LTC1742, LTC1744, LTC1746 Pin Compatible with the LTC1749 Rail-to-Rail Input and Output DC to 3GHz, 17dBm IIP3, Integrated LO Buffer 1.5GHz to 2.5GHz, 21.5dBm IIP3, Integrated LO Quadrature Generator 800MHz to 3GHz, 17dBm IIP3, Integrated LO Buffer 600MHz to 3GHz, 25dBm IIP3, Integrated LO Buffer
1749f
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 0204 1K * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

▲Up To Search▲

Price & Availability of LTC1749IFW

	To Download LTC1749IFW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .